1. Field of the Invention
This invention relates generally to complementary Metal Oxide Semiconductor Field Effect transistor (CMOSFET) memory devices and, more particularly, relates to an improved address decoder for CMOS random access memories and the like.
2. Description of the Prior Art
CMOS memory devices consisting of P channel MOSFET and N channel MOSFET are well-known; there are two types that is to say the dynamic type memory device and the static type memory device. But the static type memory device is mostly used, because of the low power consumption, and recently large scale semiconductor memories such as 1 K bits memories have been developed. In many cases, a plurality of the abovementioned memory devices are combined to obtain a large scale semiconductor memory apparatus.
Now, as regards the complementary MOSFET circuits, there are many cases in which the switching characteristics become slow as compared with MOS N channel or P channel type MOS circuits. Now, the access time t.sub.ACC of a semiconductor memory device can be regarded as the sum of the propagation delays of the various circuit blocks making up the memory device, and can be expressed by the following equation, EQU t.sub.ACC = A(t) + C(t) + S(t) + O(t) (1)
In this equation, A(t) is the propagation delay of the address line and decoder circuit, C(t) is the time for data read-out to the common bus line of the memory cells, S(t) is a time dependent on the sense sensitivity of the sense circuit and O(t) is the delay time in the output circuit.
Now, two conventional types of CMOS address decoder circuits are known. Firstly, a static type one is constructed with load MOS transistors connected in parallel and switching MOS transistors connected in series, and decoder inputs are applied to the gate electrodes of the switching MOS transistors. Secondly, a semidynamic type one comprises a load MOS transistor for static operation, a precharge MOS transistor for dynamic operation and switching MOS transistors connected in series, and the decoder inputs are applied to the gate electrodes of the switching transistors.
Thus, the abovementioned two types of the decoder circuits are AND circuits in which when these circuits are set up, the imparted charge is discharged through multi-stage series MOS transistors, and therefore the set-up time during which the decoder circuits are being set up becomes long and causes A(t) in Equation (1) to increase. Furthermore, as the number of memory bits increases, the number of stages in the decoder input becomes greater and the decoder set-up time unavoidably becomes progressively longer.